Generally, complementary metal oxide-semiconductor (CMOS) transistors include a gate electrode and a gate dielectric, which are formed on a substrate (usually a silicon semiconductor substrate). Lightly doped drains are formed on opposing sides of the gate electrode by implanting N-type or P-type impurities into the substrate. An oxide liner and one or more implant masks (commonly referred to as spacers) are formed adjacent the gate electrode, and additional implants are performed to complete the source/drain regions. Current flowing through the source/drain regions may then be controlled by controlling the voltage levels applied to the gate electrode.
Reduction in the size of CMOS transistors has provided continued improvement in speed, performance, circuit density, and cost per unit function over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, the source and drain increasingly interact with the channel and gain influence on the channel potential. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate to substantially control the on and off states of the channel.